Publications

• Year of 2000
  • W.S. Mak, C.F. Chan, K.W. Cheung and C.S. Choy, "An 8x8 Adiabatic Quasi-Static CMOS Multiplier", Proceedings of IEEE Symposium on Circuits and Systems, May 2000, pp. V553-V556.

  • Tin-Yau Tang, Chiu-Sing Choy, Jan Butas and Cheong-Fat Chan, "An ALU Design using a Novel Asynchronous Pipeline Architecture", Proceedings of IEEE Symposium on Circuits and Systems, May 2000, pp. V361-V364.

  • Tin-Yau Tang, Chiu-Sing Choy, Pui-Lam Siu and Cheong-Fat Chan, "Design of Self-timed Asynchronous Booth’s multiplier", Proceedings of Asia and South Pacific Design Automation Conference, January 2000, pp. 15-16.

• Year of 1999
  • T. C. Pang, C. S. Choy, C. F. Chan, W. K. Cham, "A Self-timed 1-D ICT Chip for Image Coding", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 9. No. 6, September 1999, pp. 856-860.

  • J. Povazanec, C.S. Choy, C.F. Chan, J. Butas, Y.Q. Zhang, J.L. Yang, T.Y. Tang, "Pipelined dataflow architecture of a small processor", Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, June 1999, pp. 1217-1223.

  • J.L. Yang, C.S. Choy, C.F. Chan, "A noval ad hoc test structure for asynchronous pipeline circuits", IEEE European Test Workshop, session p.4, Constance, Germany, May 25-28, 1999

  • W.Y. Sit, C.S. Choy, C.F. Chan, "A four-phase handshaking asynchronous static RAM design for self-timed systems", IEEE Journal of Solid-State Circuits, Vol. 34, No. 1, January 1999, pp. 90-96.

• Year of 1998
  • J.L. Yang, C.S. Choy, C.F. Chan, "Fault behavior & testing of micropipeline based asynchronous designs", Proceedings of the 3rd International Conference on ASIC, October 1998, pp. 443-445.

  • C.F. Chan, K.W. Cheng, C.S. Choy, "A low-power adiabatic CMOS circuit", Proceedings of the 3rd International Conference on ASIC, October 1998, pp. 232-234.

  • C.F. Chan, K.S. Cheng, C.S. Choy, "An injection-locked clock doubling circuit", Proceedings of the 3rd International Conference on ASIC, October 1998, pp. 221-223.

  • H.W. Wang, C.F. Chan, C.S. Choy, "Sinc function interpolator using parallel and symmetrical architecture", Proceedings of the 3rd International Conference on ASIC, October 1998, pp. 101-104.

  • J. Povazanec, C.S. Choy, C.F. Chan, "Asynchronous logic in bit-serial arithmetic", Proeedings of IEEE International Conference on Electronics, Circuits and Systems, Vol. 3, September 1998, pp. 175-178.

  • C.S. Choy, T.C. Pang, J. Povazanec and C.F. Chan, "An useful micropipeline architecture to implement DSP algorithms", Proceedings of the 24th Euromicro Conference, Vol. 1, August 1998, pp. 212-215.